Toshiba H1 SERIES TLCS-900 Manuel d'utilisateur Page 232
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- Table des matières
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Noté. / 5. Basé sur avis des utilisateurs
TMP92CM22
2007-02-16
92CM22-230
[2] Interrupt controller [3] DMA controller
Address
Name Address Name Address Name Address Name
00D0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE12
INTE3
INTETA01
INTETA23
INTETB0
INTETBO0
INTES0
INTES1
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE45
INTETB1
INTETBO1
INTESB0
INTEP0
00F0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTE0AD
INTETC01
INTETC23
INTETC45
INTETC67
SIMC
IIMC
INTWDT
INTCLR
IIMC2
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
DMA0V
DMA1V
DMA2V
DMA3V
DMA4V
DMA5V
DMA6V
DMA7V
DMAB
DMAR
Reserved
[4] Memory controller [5] Clock gear/PLL
Address
Name Address Name Address Name Address Name
0140H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
B0CSL
B0CSH
MAMR0
MSAR0
B1CSL
B1CSH
MAMR1
MSAR1
B2CSL
B2CSH
MAMR2
MSAR2
B3CSL
B3CSH
MAMR3
MSAR3
0150H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
BEXCSL
BEXCSH
0160H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
PMEMCR
10E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
EMCCR2
Reserved
PLLCR
Reserved
- TLCS-900/H1 Series 1
- Preface 2
- TMP92CM22FG 3
- 92CM22-2 4
- 92CM22-3 5
- 2.1 Pin Assignment 6
- 2.2 Pin Names and Functions 7
- 92CM22-6 8
- 3.1 CPU 9
- TMP92CM22 10
- 2007-02-16 10
- 92CM22-8 10
- 3.1.2 Reset Operation 10
- 92CM22-9 11
- 3.2 Memory Map 12
- 92CM22-11 13
- 92CM22-12 14
- 92CM22-13 15
- 92CM22-14 16
- 3.3.2 SFRs 16
- 92CM22-15 17
- 92CM22-16 18
- 92CM22-17 19
- 3.3.4 Clock Doubler (PLL) 19
- 92CM22-18 20
- 92CM22-19 21
- 92CM22-20 22
- (Double key) 23
- 92CM22-22 24
- 3.3.6 Standby Controller 24
- 92CM22-23 25
- 92CM22-24 26
- 92CM22-25 27
- = 10 MHz 28
- 92CM22-27 29
- 92CM22-28 30
- 3.4 Interrupt 31
- 92CM22-30 32
- 92CM22-31 33
- 92CM22-32 34
- 92CM22-33 35
- 92CM22-34 36
- 3.4.2 Micro DMA 36
- 92CM22-35 37
- 92CM22-36 38
- 92CM22-37 39
- 92CM22-38 40
- 92CM22-39 41
- 92CM22-40 42
- 92CM22-41 43
- 92CM22-42 44
- 92CM22-43 45
- 92CM22-44 46
- 92CM22-45 47
- 92CM22-46 48
- 0 0 0 0 0 0 0 0 49
- DMAB DMA burst 108H 49
- 1: DMA request on burst mode 49
- 92CM22-48 50
- 3.5 Port Function 51
- 92CM22-50 52
- 92CM22-51 53
- 92CM22-52 54
- 3.5.1 Port 1 (P10 to P17) 54
- 92CM22-53 55
- 92CM22-54 56
- 3.5.2 Port 4 (P40 to P47) 56
- 92CM22-55 57
- 92CM22-56 58
- 3.5.3 Port 5 (P50 to P57) 58
- 92CM22-57 59
- 92CM22-58 60
- 3.5.4 Port 6 (P60 to P67) 60
- 92CM22-59 61
- RD , WRLL 62
- 92CM22-61 63
- 92CM22-62 64
- 3.5.6 Port 8 (P80 to P83) 64
- Open-drain enable 65
- P9ODE<P91ODE> 65
- <P92ODE> 65
- 0: Port 66
- SCK input 66
- 1:SCK output 66
- Data from 67
- 92CM22-66 68
- Select rising/falling 69
- 92CM22-68 70
- 92CM22-69 71
- 92CM22-70 72
- 3.5.10 Port D (PD0 to PD3) 72
- 92CM22-71 73
- 92CM22-72 74
- 92CM22-73 75
- 3.5.11 Port F (PF0 to PF7) 75
- 92CM22-74 76
- CTS input 77
- <PF3C> 78
- <PF3F> 78
- <PF0C> 78
- <PF0F> 78
- 92CM22-77 79
- 3.5.12 Port G (PG0 to PG7) 79
- 0 waits, 1 wait 80
- 2 waits, 3 waits, 4 waits 80
- 0 0 Don’t use this setting 81
- 1 1 Don’t use this setting 81
- 92CM22-80 82
- CS1 is set to “low” 83
- 92CM22-82 84
- 92CM22-83 85
- 92CM22-84 86
- 92CM22-85 87
- 92CM22-86 88
- 92CM22-87 89
- WAIT input cycle (5 waits) 90
- 92CM22-89 91
- 92CM22-90 92
- 92CM22-91 93
- 3.6.5 List of Registers 93
- 92CM22-92 94
- WAIT pin input mode 95
- 92CM22-94 96
- 92CM22-95 97
- 92CM22-96 98
- 92CM22-97 99
- 3.6.6 Caution 99
- 92CM22-98 100
- 3.7 8-Bit Timers (TMRA) 101
- 92CM22-100 102
- 3.7.1 Block Diagrams 102
- 92CM22-101 103
- 92CM22-102 104
- 92CM22-103 105
- 92CM22-104 106
- 92CM22-105 107
- 3.7.3 SFRs 107
- Overflow output for TMRA0 108
- (16-bit timer mode) 108
- 92CM22-107 109
- 92CM22-108 110
- 92CM22-109 111
- 92CM22-110 112
- Operation in Each Mode 113
- 92CM22-112 114
- 92CM22-113 115
- 92CM22-114 116
- 92CM22-115 117
- 92CM22-116 118
- 92CM22-117 119
- 92CM22-118 120
- 92CM22-119 121
- 92CM22-120 122
- 92CM22-121 123
- 3.8.1 Block Diagram 123
- 92CM22-122 124
- 92CM22-123 125
- 3.8.2 Operation 125
- 92CM22-124 126
- 92CM22-125 127
- 92CM22-126 128
- 92CM22-127 129
- 3.8.3 SFRs 129
- 92CM22-128 130
- 92CM22-129 131
- 92CM22-130 132
- 92CM22-131 133
- 92CM22-132 134
- 92CM22-133 135
- 92CM22-134 136
- 92CM22-135 137
- 92CM22-136 138
- 92CM22-137 139
- 92CM22-138 140
- 92CM22-139 141
- 92CM22-140 142
- 3.9 Serial Channels (SIO) 143
- 92CM22-142 144
- SCLK0 output 145
- SCLK0 input 145
- SCLK1 output 146
- SCLK1 input 146
- 92CM22-145 147
- 92CM22-146 148
- 92CM22-147 149
- 92CM22-148 150
- 92CM22-149 151
- 92CM22-150 152
- 92CM22-151 153
- 92CM22-152 154
- 92CM22-153 155
- 92CM22-154 156
- 3.9.3 SFRs 156
- 92CM22-155 157
- 92CM22-156 158
- 92CM22-157 159
- 92CM22-158 160
- 92CM22-159 161
- 92CM22-160 162
- 92CM22-161 163
- 92CM22-162 164
- 92CM22-163 165
- 92CM22-164 166
- 92CM22-165 167
- 92CM22-166 168
- 92CM22-167 169
- 92CM22-168 170
- Transmission 171
- 92CM22-170 172
- 92CM22-171 173
- 92CM22-172 174
- 3.10.1 Configuration 174
- W : Direction bit 175
- 92CM22-174 176
- 3.10.4 I 176
- C Bus Mode Control Register 176
- 92CM22-175 177
- 92CM22-176 178
- 92CM22-177 179
- 92CM22-178 180
- 3.10.5 Control in I 180
- C Bus Mode 180
- 92CM22-179 181
- W ) sent from the master 182
- 92CM22-181 183
- 92CM22-182 184
- 92CM22-183 185
- 92CM22-184 186
- 3.10.6 Data Transfer in I 186
- 92CM22-185 187
- 92CM22-186 188
- 92CM22-187 189
- 92CM22-188 190
- 92CM22-189 191
- 00: Transmit mode 192
- 01: (Reserved) 192
- 10: Transmit/receive mode 192
- 11: Receive mode 192
- 92CM22-191 193
- 92CM22-192 194
- 92CM22-193 195
- 92CM22-194 196
- 92CM22-195 197
- 92CM22-196 198
- 92CM22-197 199
- 92CM22-198 200
- 92CM22-199 201
- 92CM22-200 202
- 92CM22-201 203
- 92CM22-202 204
- 92CM22-203 205
- 92CM22-204 206
- 92CM22-205 207
- 92CM22-206 208
- 92CM22-207 209
- 92CM22-208 210
- 92CM22-209 211
- 92CM22-210 212
- 92CM22-211 213
- 3.12.1 Configuration 213
- BUSAK goes low) 214
- 92CM22-213 215
- 3.12.3 Control Registers 215
- 92CM22-214 216
- 92CM22-215 217
- 92CM22-216 218
- 92CM22-217 219
- 92CM22-218 220
- 4.2.1 Basis Bus Cycle 220
- 92CM22-219 221
- 92CM22-220 222
- 92CM22-221 223
- 92CM22-222 224
- 4.2.2 Page ROM Read Cycle 224
- 92CM22-223 225
- 92CM22-224 226
- + 40 240 32040 227
- + 100 500 8X + 100 227
- 92CM22-226 228
- −40 to +85 229
- 92CM22-228 230
- 92CM22-229 231
- 92CM22-230 232
- 92CM22-231 233
- 92CM22-232 234
- 92CM22-233 235
- 92CM22-234 236
- 92CM22-235 237
- 92CM22-236 238
- 92CM22-237 239
- 92CM22-238 240
- 0: Disable 241
- 1: Enable 241
- Wait number on page 241
- 92CM22-240 242
- 92CM22-241 243
- 92CM22-242 244
- 92CM22-243 245
- 0: SCLK0↑ 246
- 1: SCLK0↓ 246
- Receive 246
- 0: SCLK1↑ 247
- 1: SCLK1↓ 247
- AL/SBIM1 248
- 92CM22-247 249
- 92CM22-248 250
- 92CM22-249 251
- 92CM22-250 252
- CTS0 ) 253
- CS2 ), and P83 ( CS3 ) 254
- 92CM22-253 255
- 92CM22-254 256
- 92CM22-255 257
- 92CM22-256 258
- 8. Package Dimensions 259
- 92CM22-258 260
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