Toshiba H1 SERIES TLCS-900 Manuel d'utilisateur

TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CM22FG Semiconductor Company

TMP92CM22 2007-02-16 92CM22-8 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the o

TMP92CM22 2007-02-16 92CM22-98 (2) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combina

TMP92CM22 2007-02-16 92CM22-99 3.7 8-Bit Timers (TMRA) The TMP92CM22 features 4 built-in 8-bit timers. These timers are paired into four modules: TMRA

TMP92CM22 2007-02-16 92CM22-100 3.7.1 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram φT1

TMP92CM22 2007-02-16 92CM22-101 Figure 3.7.2 TMRA23 Block Diagram φT1φT16φT2568-bit compar

TMP92CM22 2007-02-16 92CM22-102 3.7.2 Operation of Each Circuit (1) Prescaler A 9-bit prescaler generates the input clock to TMRA01. The prescaler’s

TMP92CM22 2007-02-16 92CM22-103 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the

TMP92CM22 2007-02-16 92CM22-104 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If the

TMP92CM22 2007-02-16 92CM22-105 3.7.3 SFRs 7 6 5 4 3 2 1 0 Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUNRead/Write R/W R/W Aft

TMP92CM22 2007-02-16 92CM22-106 7 6 5 4 3 2 1 0 Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0Read/Write R/W After reset

TMP92CM22 2007-02-16 92CM22-107 7 6 5 4 3 2 1 0 Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0Read/Write R/W After reset

TMP92CM22 2007-02-16 92CM22-9 Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit ex

TMP92CM22 2007-02-16 92CM22-108 7 6 5 4 3 2 1 0 Bit symbol TA1FFC1 TA1FFC0 TA1FFCIE TA1FFCISRead/Write R/W After reset 1 1 0 0 Functio

TMP92CM22 2007-02-16 92CM22-109 TMRA3 Flip-Flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TA3FFC1 TA3FFC0 TA3FFCIE TA3FFCISRead/Write R

TMP92CM22 2007-02-16 92CM22-110 Symbol Address 7 6 5 4 3 2 1 0 − W TA0REG 1102H Undefined − W TA1REG 1103H Undefined − W TA2REG 110AH Undefin

TMP92CM22 2007-02-16 92CM22-111 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval t

TMP92CM22 2007-02-16 92CM22-112 2. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant in

TMP92CM22 2007-02-16 92CM22-113 3. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator

TMP92CM22 2007-02-16 92CM22-114 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up-counter UC

TMP92CM22 2007-02-16 92CM22-115 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC

TMP92CM22 2007-02-16 92CM22-116 Example: To generate 1/4 duty 62.5 kHz pulses (at fC= 40 MHz): Calculate the value that should be set in the ti

TMP92CM22 2007-02-16 92CM22-117 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with

TMP92CM22 2007-02-16 92CM22-10 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. Figure 3.2.1 Memory Map Note 1: Wh

TMP92CM22 2007-02-16 92CM22-118 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG

TMP92CM22 2007-02-16 92CM22-119 Table 3.7.4 Relationship of PWM Cycle and 2n Counter PWM cycle TAxxMOD<PWMx1:0> 26 (x64) 27(x128) 28(x256)

TMP92CM22 2007-02-16 92CM22-120 3.8 16-Bit Timer/Event Counters (TMRB) The TMP92CM22 contains 2 channels 16-bit timer/event counter (TMRB) which hav

TMP92CM22 2007-02-16 92CM22-121 3.8.1 Block Diagram Figure 3.8.1 Block Diagram of TMRB0 Captu

TMP92CM22 2007-02-16 92CM22-122 Figure 3.8.2 Block Diagram of TMRB1 Timer flip-flop control

TMP92CM22 2007-02-16 92CM22-123 3.8.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is a

TMP92CM22 2007-02-16 92CM22-124 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the

TMP92CM22 2007-02-16 92CM22-125 (4) Capture registers (TB0CP0H/L, TB0CP1H/L, TB1CP0H/L and TB1CP1H/L) These 16-bit registers are used to latch the va

TMP92CM22 2007-02-16 92CM22-126 (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 w

TMP92CM22 2007-02-16 92CM22-127 3.8.3 SFRs TMRB0 Run Register 7 6 5 4 3 2 1 0 Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUNTB0RUN (1180H) Read/Wr

TMP92CM22 2007-02-16 92CM22-11 3.3 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reduci

TMP92CM22 2007-02-16 92CM22-128 TMRB0 Mode Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0TB0MOD (1182H)

TMP92CM22 2007-02-16 92CM22-129 TMRB1 Mode Register 7 6 5 4 3 2 1 0 Bit symbol TB1CT1 TB1ET1 TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0TB1M

TMP92CM22 2007-02-16 92CM22-130 TMRB0 Flip-flop Control Register 7 6 5 4 3 2 1 0 Bit symbol − − TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FFC1 TB0FFC0

TMP92CM22 2007-02-16 92CM22-131 TMRB1 Flip-flop Control Register 7 6 5 4 3 2 1 0 Bit symbol TB1FF1C1 TB1FF1C0 TB1C1T1 TB1C0T1 TB1E1T1 TB1E0T1

TMP92CM22 2007-02-16 92CM22-132 TMRB0 register 7 6 5 4 3 2 1 0 bit Symbol − Read/Write W TB0RG0L (1188H) After reset Undefined bit Symbol − Rea

TMP92CM22 2007-02-16 92CM22-133 3.8.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals in this example

TMP92CM22 2007-02-16 92CM22-134 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and d

TMP92CM22 2007-02-16 92CM22-135 The following block diagram illustrates this mode. Figure 3.8.11 Block Diagram of 16-Bit PPG Mo

TMP92CM22 2007-02-16 92CM22-136 (4) Capture function examples Used capture function, they can be applicable in many ways, for example: 1. One-shot pu

TMP92CM22 2007-02-16 92CM22-137 Example: To output a 2 [ms] one-shot pulse with a 3 [ms] delay to the external trigger pulse via the TB1IN0 pin.

TMP92CM22 2007-02-16 92CM22-12 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins

TMP92CM22 2007-02-16 92CM22-138 Figure 3.8.13 One-shot Pulse Output (without delay) 2. Frequency measurement The frequency of the ext

TMP92CM22 2007-02-16 92CM22-139 3. Pulse width measurement This mode allows measuring the high level width of an external pulse. While keeping the 16-

TMP92CM22 2007-02-16 92CM22-140 4. Measurement of difference time This mode is used to measure the difference in time between the rising edges of ext

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TMP92CM22 2007-02-16 92CM22-13 3.3.1 Block Diagram of System Clock Figure 3.3.2 Block Diagram of Dual Clock and System Clock

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TMP92CM22 2007-02-16 92CM22-14 3.3.2 SFRs 7 6 5 4 3 2 1 0 Bit symbol − − Read/Write R/W R/W After reset 1 0 Function Always

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TMP92CM22 2007-02-16 92CM22-15 7 6 5 4 3 2 1 0 Bit symbol PLLON FCSEL LWUPFG Read/Write R/W R After reset 0 0 0 Function 0: PL

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TMP92CM22 2007-02-16 92CM22-172 3.10 Serial Bus Interface (SBI) The TMP92CM22 has a 1-channel serial bus interface. Serial bus interface (SBI0) inclu

TMP92CM22 2007-02-16 92CM22-173 3.10.2 Control The following registers are used to control the serial bus interface and monitor the operation status.

TMP92CM22 2007-02-16 92CM22-174 3.10.4 I2C Bus Mode Control Register The following registers are used to control and monitor the operation status when

TMP92CM22 2007-02-16 92CM22-175 Serial Bus Interface Control Register 2 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN SBIM1 SBIM0 SWRST1 SWRST0SBI0

TMP92CM22 2007-02-16 92CM22-176 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Bit symbol MST TRX BB PIN AL AAS AD0 LRB SBI0SR (1243H) Re

TMP92CM22 2007-02-16 92CM22-177 Serial Bus Interface Baud Rate Register 0 7 6 5 4 3 2 1 0 Bit symbol − I2SBI0 SBI0BR0 (1244H) Read/Write W

TMP92CM22 2007-02-16 92CM22-16 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and

TMP92CM22 2007-02-16 92CM22-178 3.10.5 Control in I2C Bus Mode (1) Acknowledge mode specification Set the SBI0CR1<ACK> to 1 for operation in t

TMP92CM22 2007-02-16 92CM22-179 2. Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock li

TMP92CM22 2007-02-16 92CM22-180 (6) Transmitter/receiver selection Set the SBI0CR2<TRX> to “1” for operating the TMP92CM22 as a transmitter. Cle

TMP92CM22 2007-02-16 92CM22-181 (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request 0 (INTSBE0) o

TMP92CM22 2007-02-16 92CM22-182 The TMP92CM22 compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of th

TMP92CM22 2007-02-16 92CM22-183 (14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is rocked by

TMP92CM22 2007-02-16 92CM22-184 3.10.6 Data Transfer in I2C Bus Mode (1) Device initialization In first, set the SBI0BR1<P4EN>, SBI0CR1<ACK,

TMP92CM22 2007-02-16 92CM22-185 Figure 3.10.13 Start Condition and Slave Address Generation (3) 1-word data transfer Check the <MST&

TMP92CM22 2007-02-16 92CM22-186 When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <

TMP92CM22 2007-02-16 92CM22-187 2. If <MST> = 0 (Slave mode) In the slave mode the TMP92CM22 operates either in normal slave mode or in slave mo

TMP92CM22 2007-02-16 92CM22-17 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A reset initializes

TMP92CM22 2007-02-16 92CM22-188 (4) Stop condition generation When SBI0SR<BB> = 1, the sequence for generating a stop condition is started by w

TMP92CM22 2007-02-16 92CM22-189 (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfe

TMP92CM22 2007-02-16 92CM22-190 3.10.7 Clocked-synchronous 8-bit SIO Mode Control The following registers are used to control and monitor the operati

TMP92CM22 2007-02-16 92CM22-191 Serial Bus Interface 0 Control Register 2 7 6 5 4 3 2 1 0 Bit symbol SBIM1 SBIM0 − − SBI0CR2 (1243H) Read/

TMP92CM22 2007-02-16 92CM22-192 (1) Serial Clock 1. Clock source SBI0CR1<SCK2:0> is used to select the following functions: Internal clock In in

TMP92CM22 2007-02-16 92CM22-193 2. Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shi

TMP92CM22 2007-02-16 92CM22-194 (2) Transfer modes The SBI0CR1<SIOM1:0> is used to select a transmit, receive or transmit/receive mode. 1. 8-bi

TMP92CM22 2007-02-16 92CM22-195 Figure 3.10.25 Transmission Mode Example: Program to stop data transmission (w

TMP92CM22 2007-02-16 92CM22-196 Figure 3.10.26 Transmission Data Hold Time at End Transmit 2. 8-bit receive mode Set the control register

TMP92CM22 2007-02-16 92CM22-197 Figure 3.10.27 Receiver Mode (Example: Internal clock) 3. 8-bit transmit/receive mode Set a control

Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restric

TMP92CM22 2007-02-16 92CM22-18 Example 2: PLL stopping PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR),

TMP92CM22 2007-02-16 92CM22-198 Figure 3.10.28 Transmission/Receiving Mode (when an external clock is used) Figure 3.

TMP92CM22 2007-02-16 92CM22-199 3.11 Analog/Digital Converter The TMP92CM22 incorporates a 10-bit successive approximation-type analog/digital convert

TMP92CM22 2007-02-16 92CM22-200 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the three AD mode control registers: ADMO

TMP92CM22 2007-02-16 92CM22-201 AD Mode Control Register 1 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD − − − ADCH2 ADCH1 ADCH0 ADMOD1 (12B9H) Read/

TMP92CM22 2007-02-16 92CM22-202 AD Conversion Result Register 0 Low 7 6 5 4 3 2 1 0 Bit symbol ADR01 ADR00 ADR0RFADREG0L (12A0H) Read/Writ

TMP92CM22 2007-02-16 92CM22-203 AD Conversion Result Register 2 Low 7 6 5 4 3 2 1 0 Bit symbol ADR21 ADR20 ADR2RFADREG2L (12A4H) Read/Writ

TMP92CM22 2007-02-16 92CM22-204 AD Conversion Result Register 4 Low 7 6 5 4 3 2 1 0 Bit symbol ADR41 ADR40 ADR4RFADREG4L (12A8H) Read/Writ

TMP92CM22 2007-02-16 92CM22-205 AD Conversion Result Register 6 Low 7 6 5 4 3 2 1 0 Bit symbol ADR61 ADR60 ADR6RFADREG6L (12ACH) Read/Writ

TMP92CM22 2007-02-16 92CM22-206 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the

TMP92CM22 2007-02-16 92CM22-207 (3) Starting AD conversion To start AD conversion, program “1” to ADMOD0<ADS> in AD mode control register 0, or

TMP92CM22 2007-02-16 92CM22-19 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and

TMP92CM22 2007-02-16 92CM22-208 3. Channel fixed repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to “10” selects conversio

TMP92CM22 2007-02-16 92CM22-209 (5) AD conversion time 84 states (8.4 μs at fSYS = 20 MHz) are required for the AD conversion of one channel. (6) St

TMP92CM22 2007-02-16 92CM22-210 Example: 1. Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the A

TMP92CM22 2007-02-16 92CM22-211 3.12 Watchdog Timer (Runaway detection timer) The TMP92CM22 contains a watchdog timer of runaway detecting. The watch

TMP92CM22 2007-02-16 92CM22-212 3.12.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0&g

TMP92CM22 2007-02-16 92CM22-213 3.12.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog

TMP92CM22 2007-02-16 92CM22-214 7 6 5 4 3 2 1 0 Bit symbol WDTE WDTP1 WDTP0 − I2WDT RESCR − WDMOD (1300H) Read/Write R/W R/W After res

TMP92CM22 2007-02-16 92CM22-215 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage Vcc

TMP92CM22 2007-02-16 92CM22-216 DC Characteristics (1/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Symbol Condition Min Typ. M

TMP92CM22 2007-02-16 92CM22-217 DC Characteristics (2/2) Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C Parameter Symbol Condition Min Typ. Ma

TMP92CM22 2007-02-16 92CM22-20 (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted

TMP92CM22 2007-02-16 92CM22-218 4.2 AC Characteristics 4.2.1 Basis Bus Cycle Read cycle Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C No. Param

TMP92CM22 2007-02-16 92CM22-219 (1) Read cycle (0 waits, fc = fOSCH, fFPH = fc/1) Note: The phase relation between X1 input sig

TMP92CM22 2007-02-16 92CM22-220 (2) Write cycle (0 waits, fc = fOSCH, fFPH = fc/1) Note: The phase relation between X1 input sig

TMP92CM22 2007-02-16 92CM22-221 (3) Read cycle (1 wait) (4) Write cycle (1 wait) A0 to A23 WAITData input tRD3tRR3tAD3CL

TMP92CM22 2007-02-16 92CM22-222 4.2.2 Page ROM Read Cycle (1) 3-2-2-2 mode Vcc = 3.3 ± 0.3 V/fc = 4 to 40 MHz/Ta = −40 to 85°C No. Parameter Symbol M

TMP92CM22 2007-02-16 92CM22-223 4.3 AD Conversion Characteristics Parameter Symbol Min Typ. Max Unit Analog reference voltage (+) VREFH VCC − 0.2 VCC

TMP92CM22 2007-02-16 92CM22-224 4.5 Serial Channel Timing (I/O interface mode) Note: Symbol “X” in the following table means the period of clock “fS

TMP92CM22 2007-02-16 92CM22-225 4.6 Interrupt, Capture Note: Symbol “X” in the following table means the period of clock “fSYS”, it’s s

TMP92CM22 2007-02-16 92CM22-226 4.7 Recommended Oscillation Circuit TMP92CM22 is evaluated by below oscillator vender. When selecting external parts,

TMP92CM22 2007-02-16 92CM22-227 (2) TMP92CM22 recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Following table shows circuit parameter r

TMP92CM22 2007-02-16 92CM22-21 (3) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write op

TMP92CM22 2007-02-16 92CM22-228 5. Table of Special Function Registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocat

TMP92CM22 2007-02-16 92CM22-229 Table 5.1 I/O Register Address Map [1] I/O port Address Name Address Name Address Name Address Name 0000H 1H 2H 3H 4H

TMP92CM22 2007-02-16 92CM22-230 [2] Interrupt controller [3] DMA controller Address Name Address Name Address Name Address Name 00D0H 1H 2H 3H 4H 5

TMP92CM22 2007-02-16 92CM22-231 [6] 8-bit timer [7] 16-bit timer [8] UART/SIO Address Name Address Name Address Name Address Name 1100H 1H 2H 3H

TMP92CM22 2007-02-16 92CM22-232 (1) I/O port (1/3) Symbol Name Address 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 Port 1 0004H Data from

TMP92CM22 2007-02-16 92CM22-233 I/O port (2/3) Symbol Name Address 7 6 5 4 3 2 1 0 P17C P16C P15C P14C P13C P12C P11C P10C W 0 0 0 0 0 0 0 0 P1CR Port

TMP92CM22 2007-02-16 92CM22-234 I/O port (3/3) Symbol Name Address 7 6 5 4 3 2 1 0 P92C P91C P90C W 0 0 0 P9CR Port 9 control register

TMP92CM22 2007-02-16 92CM22-235 (2) Interrupt control (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2 I1M1 I1M0 R R/W

TMP92CM22 2007-02-16 92CM22-236 Interrupt control (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 − INTP0 − − − − IP0C IP0M2 IP0M1 IP0M0 − − − − R R/

TMP92CM22 2007-02-16 92CM22-237 (3) DMA controller Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0

TMP92CM22 2007-02-16 92CM22-22 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, ID

TMP92CM22 2007-02-16 92CM22-238 (4) Memory controller (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 W W 0 1 0 0

TMP92CM22 2007-02-16 92CM22-239 Memory controller (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0 W W 0 1 0

TMP92CM22 2007-02-16 92CM22-240 (5) Clock gear Symbol Name Address 7 6 5 4 3 2 1 0 − − R/W R/W 1 0 SYSCR0 System clock control 0 10

TMP92CM22 2007-02-16 92CM22-241 (6) 8-bit timer Symbol Name Address 7 6 5 4 3 2 1 0 TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUNR/W R/W 0 0 0 0 0

TMP92CM22 2007-02-16 92CM22-242 (7) 16-bit timer (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB0RDE − I2TB0 TB0PRUN TB0RUNR/W R/W R/W 0 0 0

TMP92CM22 2007-02-16 92CM22-243 16-bit timer (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 TB1RDE − I2TB0 TB1PRUN TB1RUNR/W R/W R/W 0 0 0 0 0

TMP92CM22 2007-02-16 92CM22-244 (8) UART/Serial channel (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB

TMP92CM22 2007-02-16 92CM22-245 UART/Serial channel (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1

TMP92CM22 2007-02-16 92CM22-246 (9) I2C bus/Serial channel (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 BC2 BC1 BC0 ACK SCK2 SCK1 SCK0/ SWRMONW R/W

TMP92CM22 2007-02-16 92CM22-247 I2C bus/Serial channel (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 − I2SBI0 W R/W 0 0 1244H (I2C mode

TMP92CM22 2007-02-16 92CM22-23 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt r

TMP92CM22 2007-02-16 92CM22-248 (10) AD converter (1/2) Symbol Name Address 7 6 5 4 3 2 1 0 EOCF ADBF − − ITM0 REPEAT SCAN ADS R R/W 0 0 0 0 0 0 0

TMP92CM22 2007-02-16 92CM22-249 AD converter (2/2) Symbol Name Address 7 6 5 4 3 2 1 0 ADR41 ADR40 ADR4RFR R ADREG4L AD result register 4

TMP92CM22 2007-02-16 92CM22-250 (11) Watchdog timer Symbol Name Address 7 6 5 4 3 2 1 0 WDTE WDTP1 WDTP0 − I2WDT RESCR − R/W R/W 1 0 0 0 0 0

TMP92CM22 2007-02-16 92CM22-251 6. Port Section Equivalent Circuit Diagram Reading the circuit diagram Basically, the gate symbols written are th

TMP92CM22 2007-02-16 92CM22-252 P70 (RD ), P71 ( WRLL ), P72 ( WRLU ), P73, P74 (CLKOUT), P75 ( WR/ ), P80 ( CS0 ), P81 ( CS1 ), P82 (CS2 ), and P83

TMP92CM22 2007-02-16 92CM22-253 PF0 (TXD0) and PF3 (TXD1) PG0 (AN0), PG1 (AN1), PG2 (AN2), PG3 (AN3/ADTRG ), PG4 (AN4), PG5 (AN5

TMP92CM22 2007-02-16 92CM22-254 X1 and X2 VREFH and VREFL AM0 and AM1 NMI Stringresistance VREFON

TMP92CM22 2007-02-16 92CM22-255 7. Points to Note and Restrictions (1) Notation 1. The notation for built-in I/O registers is as follows register sy

TMP92CM22 2007-02-16 92CM22-256 (2) Points to note a) AM0 and AM1 pins This pin is connected to the VCC (Power supply level) or VSS (Ground level)

TMP92CM22 2007-02-16 92CM22-257 8. Package Dimensions P-LQFP100-144-0.50F Unit: mm

TMP92CM22 2007-02-16 92CM22-24 Table 3.3.3 Source of Halt State Release and Halt Release Operation Status of Received Interrupt Interrupt Enable (In

TMP92CM22 2007-02-16 92CM22-258

TMP92CM22 2007-02-16 92CM22-25 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting re

TMP92CM22 2007-02-16 92CM22-26 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in ST

TMP92CM22 2007-02-16 92CM22-27 Table 3.3.5 Input Buffer State Table Input Buffer State In HALT mode (IDLE1/STOP) Input Buffer State Input Buffer Stat

TMP92CM22 2007-02-16 92CM22-1 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high-speed advanced 32-bit

TMP92CM22 2007-02-16 92CM22-28 Table 3.3.6 Output Buffer State Table Note: Condition A/B are as follows. SYSCR2 register setting HALT mode <DRVE&g

TMP92CM22 2007-02-16 92CM22-29 3.4 Interrupt Interrupts of TLCS-900/H1 are controlled by the CPU interrupt mask flip-flop (IFF2:0) and by the built-i

TMP92CM22 2007-02-16 92CM22-30 Figure 3.4.1 Interrupt and Micro DMA Processing Sequence Interrupt processing Inte

TMP92CM22 2007-02-16 92CM22-31 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequen

TMP92CM22 2007-02-16 92CM22-32 Table 3.4.1 TMP92CM22 Interrupt Vectors and Micro DMA Start Vectors Default Priority Type Interrupt Source Vector Val

TMP92CM22 2007-02-16 92CM22-33 Default Priority Type Interrupt Source Vector Value Address Refer to Vector Micro DMA Start Vector52 INTAD: AD conver

TMP92CM22 2007-02-16 92CM22-34 3.4.2 Micro DMA In addition to general-purpose interrupt processing, the TMP92CM22 also includes a micro DMA function.

TMP92CM22 2007-02-16 92CM22-35 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wid

TMP92CM22 2007-02-16 92CM22-36 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP92CM22 includes a micro DMA

TMP92CM22 2007-02-16 92CM22-37 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAM [4:0] Operation Exe

TMP92CM22 2007-02-16 92CM22-2 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8

TMP92CM22 2007-02-16 92CM22-38 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand sid

TMP92CM22 2007-02-16 92CM22-39 Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt request signal to CPU

TMP92CM22 2007-02-16 92CM22-40 (1) Interrupt priority setting registers Symbol Name Address 7 6 5 4 3 2 1 0 INT2 INT1 I2C I2M2 I2M1 I2M0 I1C I1M2

TMP92CM22 2007-02-16 92CM22-41 Symbol Name Address 7 6 5 4 3 2 1 0 INTAD INT0 IADC IADM2 IADM1 IADM0 I0C I0M2 I0M1 I0M0 R R/W R R/W INTE0AD INT0&a

TMP92CM22 2007-02-16 92CM22-42 (2) External interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE W R/W

TMP92CM22 2007-02-16 92CM22-43 Table 3.4.2 Function Setting of External Interrupt Pin Interrupt Pin Shared Pin Mode Setting Method Rising edge

TMP92CM22 2007-02-16 92CM22-44 (3) SIO receive interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 IR1LE IR0LE W 1 1 SIMC S

TMP92CM22 2007-02-16 92CM22-45 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA s

TMP92CM22 2007-02-16 92CM22-46 Symbol Name Address 7 6 5 4 3 2 1 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 DMA0V DMA0 start v

TMP92CM22 2007-02-16 92CM22-47 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started

TMP92CM22 2007-02-16 92CM22-3 Figure 1.1 TMP92CM22 Block Diagram XSP XIZ XIY XIX XHL XDE XBC XWA 900/H1 CPU F SR32 bitsIX IY IZ SP LHEDCBAWP C 32-K

TMP92CM22 2007-02-16 92CM22-48 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, im

TMP92CM22 2007-02-16 92CM22-49 3.5 Port Function The TMP92CM22 features 50-bit settings which relate to the various I/O ports. As well as general-pu

TMP92CM22 2007-02-16 92CM22-50 Table 3.5.2 I/O Port Setting List (1/2) I/O Register Setting Value Ports Input Pins Specification Pn PnCR PnFC PnODEI

TMP92CM22 2007-02-16 92CM22-51 Table 3.5.3 I/O Port Setting List (2/2) I/O Register Setting Value Ports Input Pins Specification Pn PnCR PnFC PnODEP

TMP92CM22 2007-02-16 92CM22-52 3.5.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or

TMP92CM22 2007-02-16 92CM22-53 Port 1 Register 7 6 5 4 3 2 1 0 Bit symbol P17 P16 P15 P14 P13 P12 P11 P10 Read/Write R/W After reset Data from ext

TMP92CM22 2007-02-16 92CM22-54 3.5.2 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs

TMP92CM22 2007-02-16 92CM22-55 Port 4 Register 7 6 5 4 3 2 1 0 Bit symbol P47 P46 P45 P44 P43 P42 P41 P40 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-56 3.5.3 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs

TMP92CM22 2007-02-16 92CM22-57 Port 5 Register 7 6 5 4 3 2 1 0 Bit symbol P57 P56 P55 P54 P53 P52 P51 P50 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-4 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are

TMP92CM22 2007-02-16 92CM22-58 3.5.4 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port*. Bits can be individually set as either inputs

TMP92CM22 2007-02-16 92CM22-59 Port 6 Register 7 6 5 4 3 2 1 0 Bit symbol P67 P66 P65 P64 P63 P62 P61 P60 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-60 3.5.5 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70 to P75 are used for output only). Bits can

TMP92CM22 2007-02-16 92CM22-61 Figure 3.5.10 Port 7 (P76) Port 7 Register 7 6 5 4 3 2 1 0 Bit symbol P76 P75 P74 P

TMP92CM22 2007-02-16 92CM22-62 3.5.6 Port 8 (P80 to P83) Port 8 is 4-bit output port. Resetting sets output latch of P82 to “0” and set output latch

TMP92CM22 2007-02-16 92CM22-63 3.5.7 Port 9 (P90 to P92) Port 9 is 3-bit general-purpose I/O port. Each bit can be set individually for input or outp

TMP92CM22 2007-02-16 92CM22-64 Port 9 Register 7 6 5 4 3 2 1 0 Bit symbol P92 P91 P90 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-65 3.5.8 Port A (PA0 to PA2, PA7) Port A is 4-bit general-purpose input port with pull-up resistor. Figure 3.5.16 Por

TMP92CM22 2007-02-16 92CM22-66 3.5.9 Port C (PC0, PC1, PC3, PC5, and PC6) Port C is 5-bit general-purpose I/O port. Each bit can be set individually

TMP92CM22 2007-02-16 92CM22-67 (2) PC1 (INT1, TA1OUT), PC5 (INT2, TA3OUT), PC6 (INT3, TB0OUT0) In addition to function as I/O port, port PC1, PC5, and

TMP92CM22 2007-02-16 92CM22-5 2.2 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 P

TMP92CM22 2007-02-16 92CM22-68 (3) PC3 (INT0) In addition to function as I/O port, port PC3 can also function as external interrupt pin INT0. Figure

TMP92CM22 2007-02-16 92CM22-69 Port C Register 7 6 5 4 3 2 1 0 Bit symbol PC6 PC5 PC3 PC1 PC0 Read/Write R/W R/W R/W After reset D

TMP92CM22 2007-02-16 92CM22-70 3.5.10 Port D (PD0 to PD3) Port D is 4-bit general-purpose I/O port. Each bit can be set individually for input or out

TMP92CM22 2007-02-16 92CM22-71 (2) PD2 (TB1OUT0) and PD3 (TB1OUT1) In addition to function as I/O port, port PD0 and PD1 can also function as timer c

TMP92CM22 2007-02-16 92CM22-72 Port D Register 7 6 5 4 3 2 1 0 Bit symbol PD3 PD2 PD1 PD0 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-73 3.5.11 Port F (PF0 to PF7) Port F is 8-bit general-purpose I/O port. Each bit can be set individually for input or out

TMP92CM22 2007-02-16 92CM22-74 (2) Ports PF1 and PF4 (RXD0 and XD1) In addition to function as I/O port, port PF1 and PF4 can also function as RXD in

TMP92CM22 2007-02-16 92CM22-75 (3) Port PF2 (CTS0, SCLK0) and port PF5 (CTS1, SCLK1) In addition to function as I/O port, port PF2 and PF5 can also f

TMP92CM22 2007-02-16 92CM22-76 Port F Register 7 6 5 4 3 2 1 0 Bit symbol PF7 PF6 PF5 PF4 PF PF2 PF1 PF0 Read/Write R/W After reset Data from ex

TMP92CM22 2007-02-16 92CM22-77 3.5.12 Port G (PG0 to PG7) Port G is 8-bit input port and can also be used as the analog input pins for the internal

TMP92CM22 2007-02-16 92CM22-6 Table 2.2.2 Pin Names and Functions (2/2) Pin Names Number of Pins I/O Functions PC0 TA0IN 1 I/O Input Port C0: I/O po

TMP92CM22 2007-02-16 92CM22-78 3.6 Memory Controller 3.6.1 Function TMP92CM22 has a memory controller with a variable 4-block address area that contro

TMP92CM22 2007-02-16 92CM22-79 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory co

TMP92CM22 2007-02-16 92CM22-80 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the connecting memory a

TMP92CM22 2007-02-16 92CM22-81 (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register a

TMP92CM22 2007-02-16 92CM22-82 (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory

TMP92CM22 2007-02-16 92CM22-83 CPU Data Data Size (Bit) Start Address Data Width in Memory Side (Bit)CPU Address D15 to D8 D7 to D0 4n + 0 8/16 4n

TMP92CM22 2007-02-16 92CM22-84 (4) Wait control The external bus cycle completes a wait of two states at least (100 ns at fSYS = 20 MHz). Setting the

TMP92CM22 2007-02-16 92CM22-85 • When not inserting a dummy (0 waits) • When inserting a dummy cycle (0 waits) CLKOUTAddressCSmCSnRDC

TMP92CM22 2007-02-16 92CM22-86 (5) Bus access timing • External read/write bus cycle (0 waits) • External read/write bus cycle (1 wai

TMP92CM22 2007-02-16 92CM22-87 • External read/write bus cycle (0 waits at WAIT pin input mode) • External read/write bus cy

TMP92CM22 2007-02-16 92CM22-7 3. Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM

TMP92CM22 2007-02-16 92CM22-88 Example of WAIT input cycle (5 waits) D Q CK RES D Q CK RESD Q CK RESD Q CK RE

TMP92CM22 2007-02-16 92CM22-89 (6) Connecting external memory Figure 3.6.1 shows an example of how to connect external memory to the TMP92CM22. This

TMP92CM22 2007-02-16 92CM22-90 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode i

TMP92CM22 2007-02-16 92CM22-91 3.6.5 List of Registers The memory control registers and the settings are described as follows. For the addresses of t

TMP92CM22 2007-02-16 92CM22-92 B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cy

TMP92CM22 2007-02-16 92CM22-93 BEXCSL 7 6 5 4 3 2 1 0 Bit symbol BEXWW2 BEXWW1 BEXWW0 BEXWR2 BEXWR1 BEXWR0Read/Write W W After reset 0 1

TMP92CM22 2007-02-16 92CM22-94 (1) Block address area specification register A start address and range in the block address are specified by the memo

TMP92CM22 2007-02-16 92CM22-95 (2) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is ex

TMP92CM22 2007-02-16 92CM22-96 Table 3.6.1 Control Register 7 6 5 4 3 2 1 0 B0CSL Bit symbol B0WW2 B0WW1 B0WW0 B0WR2 B0WR1 B0WR0 (0140H) Read

TMP92CM22 2007-02-16 92CM22-97 3.6.6 Caution If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the chip s